Portfolio
In this section you can check some projects that I developed during my professional and academic life
Federated Learning Hardware Awareness
2021 (Ms. Thesis)
This project consisted in my Ms. Thesis. I implemented a simulator to enable the analysis of the impacts caused by hardware heterogeneity on the performance of Federated Learning tasks. During the thesis development, I acquired skills related to:
Python development
Tensorflow
Mobile edge computing networks
Scientific Writing
FPGA Neural Network Training
2020
In this project I implemented the full cycle of Convolutional neural networks training (forward and backpropagation) using a high level synthesis tool for FPGAs called OpenCL.
During this project I developed skills related to:
High Level Synthesis Tool
Software debugging in remote environments (I used Intel DevCloud to implement this project)
FPGA resource optimization
End of Program Project: Embedded Cyclocomputer
2018
As a requirement to obtain the bachelor degree at UFRN, the student has to develop a study or project to be presented as the final project of the undergraduate course.
My proposed end of program project is the development of a cyclocomputer device based on PIC microcontroller that offers innovative functionalities besides the classical cyclocomputers.
The core innovations in this system is are related to provide more security functions to the cyclist; to provide a more comprehensive monitoring on the surrounding environment that bicycles travel and to provide a smart communication capability between cyclists and central gateways.
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You can find the complete report in this link (original) or in this link (translated to english).
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PIC programming
Short-courses: 2017-2019
This was a series of short-courses (8-12h) that I thaught to people interested in low-level programming of PIC microcontrollers.
Given in a progressive hands-on style, these short courses focus on how to configure in a low-level approach the main peripheral blocks of the microcontroller. Then, in the last section, the students are able to design a small project that integrates the usage of all those peripherals.
The material for the 2019 short course is available in this link.
Hardware acceleration of Digital Image Processing operations
2018
This was the final project for the class of Special Topic in Embedded Systems at UFRN.
Following the Platform-based design methodology and using High Level Synthesis Tools (Altera dspBuilder), I proposed the implementation of some core Digital Image Processing operations that are common in Convolutional Neural Networks models, like convolution and max-pooling.
You can download the project report here.
Low-Level Implementation of Digital Image Processing Operations
2017
This was the final project for the course of Computer Architecture that I took at UFRN.
By using a low-level assembly language development approach, this project implements some basic and nice Digital Image Processing operations, like negative of a image and Steganography.
The solutions was implemented in the Assembly development environment Fresh IDE, that provides an oriented-object paradigm for assembly code. This feature eases some implementation processes, specially for Graphical Interface development.
You can access the source code here or contact me for further details.
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Hardware Platform for Data Acquisition
and Control on Photovoltaic Module
2016 - Intel Embedded System Competition
This project was developed for the 2016 Embedded System Competition, promoted by Intel, at the Brazilian Symposium on Computing Systems Engineering (SBESC).
The designed platform consist in a photovoltaic panel and several sensors to monitor critical factors
about the efficiency of the system. To achieve that, variables like irradiance, temperature,
voltage and current are being monitored. The platform also incorporates a tracking system
with a single degree of freedom. The main data processor unit is a Intel® Galileo Gen2 which
control the photovoltaic system and gather information to optimize the energy use.
Design of a basic RISC microprocessor
2016
This as the final project for the class of Digital Systems that I took at UFRN.
I implemented the hardware blocks that constitute the datapath of a basic 16-bit RISC processor, as well as the controller, using RTL methodology. The design was developed in FPGA platform using VHDL.
